Part Number Hot Search : 
AD22304 PCF85 FFM102 154K0 BR86D CJF6107 MC100LV 82537070
Product Description
Full Text Search
 

To Download PLL501-03SM Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 PLL501-01/-03
VCXO Clock Generator IC
FEATURES
* * * * * * * * Integrated voltage-controlled crystal oscillator circuitry (VCXO) (pull range 200ppm minimum). Ideal for ADSL (35.328MHz) and Set-Top Box and multimedia (27MHz) applications. VCXO tuning range: 0-3.3V. Uses inexpensive fundamental-mode parallel resonant crystals (from 10 to 20MHz). Integrated phase-locked loop (PLL) provides pullable output frequency at 2x (PLL501-01) and 4x (PLL501-03) crystal frequency. 3.3V supply voltage. Small circuit board footprint (8-pin 0.150'' SOIC). 12mA output drives capability at TTL level.
PIN CONFIGURATION
XIN VDD VIN GND 1 2 3 4 8 7 6 5 XOUT GND VDD CLK
Table 1: Crystal / Output Frequencies
DEVICE PLL501-01 PLL501-03 F XIN (MHz) 10 - 20 10 - 15 CLK (MHz) 2 x F XIN 4 x F XIN
PLL501-XX
DESCRIPTIONS
The PLL501-01 and PLL501-03 are monolithic low jitter, high performance CMOS VCXO chips. They allow the control of the output frequency with an input voltage (VIN), using a low cost crystal. While the PLL501-03 provides a pullable output clock 4 times the input crystal frequency, the PLL501-01 provides a pullable output clock 2x the input crystal frequency. This makes the PLL501-01 ideal for 35.328MHz ADSL applications (using 17.664MHz crystal) and for 27MHz Set-Top Box / multimedia applications (with a 13.5MHz crystal).
Note: Contact PhaseLink for custom PLL Frequencies
BLOCK DIAGRAM
XIN
VCXO PLL
XOUT VIN
Output Buffer
CLK
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 1
PLL501-01/-03
VCXO Clock Generator IC
PIN DESCRIPTIONS
Name XIN VDD VIN GND CLK VDD GND XOUT Number 1 2 3 4 5 6 7 8 Type I P I P O P P O Description Crystal input connection (parallel resonant crystal, C L = 10pF). 3.3V Power Supply. Voltage Input for VCXO Frequency Control. Ground for PLL Core. Clock Output. 3.3V Power Supply. Ground. Crystal connection.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 2
PLL501-01/-03
VCXO Clock Generator IC
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection SYMBOL V DD VI VO TS TA TJ V SS -0.5 V SS -0.5 -65 0 MIN. MAX. 7 V DD +0.5 V DD +0.5 150 70 125 260 2 UNITS V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. DC Electrical Specifications PARAMETERS
Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output High Voltage Output Low Voltage Output High Voltage at CMOS level Operating Supply Current Short Circuit Current VIN, VCXO Control Voltage 0
SYMBOL I DD V DD V OH V OL V OHC I DD
CONDITIONS
F XIN = 10 - 20MHz Ouput load of 10pF
MIN.
TYP.
20
MAX.
UNITS
mA
3.13 IOH = -12mA ILO = 12mA IOH = -4mA No Load V DD - 0.4 7 50 2.4
3.47
V V
0.4
V V mA mA
3.3
V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 3
PLL501-01/-03
VCXO Clock Generator IC
3. AC Electrical Specifications PARAMETERS
Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Max Absolute Jitter Short Circuit Current tr tf
SYMBOL
CONDITIONS
PLL501-01 PLL501-03 0.8V ~ 2.0V 2.0V ~ 0.8V Measured @ 1.4V Short Term
MIN.
10 10
TYP.
MAX.
20 15 1.5 1.5
UNITS
MHz ns ns % ps mA
45
50 100 50
55
4. Voltage Control Crystal Oscillator PARAMETERS
PLL Stabilization Time * VCXO Stabilization Time * Output Frequency Synthesis Error VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic
SYMBOL
T PLLSTB T VCXOSTB
CONDITIONS
From VCXO stable From power valid (Unless otherwise noted in Frequency Table) F XIN = 10 - 20MHz; XTAL C 0 /C 1 < 250; CL=10pF 0VVIN3.3V
MIN.
TYP.
500 10
MAX.
UNITS
s ms
30
ppm
200 100 100
ppm ppm ppm/V
Note: Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits.
5. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX.
20 Crystal Resonator Frequency F XIN Parallel Fundamental Mode 10
(PLL501-01)
UNITS
15
(PLL501-03)
MHz
Crystal Loading Capacitance Rating Crystal Pullability Recommended ESR
CL (xtal) C 0 /C 1 (xtal) RE AT cut AT cut
10 250 30
pF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 4
PLL501-01/-03
VCXO Clock Generator IC
6. External Components and Layout Recommendations The PLL501-01/-03 requires a minimum number of external components for proper operation. A standard low frequency decoupling capacitor of 4.7F or more should be used between VDD and GND (pin 2 and pin 4, as well as pin 6 and pin 7). Additionally, higher frequency decoupling capacitors of 0.1F are required between VDD and GND (between pin 2 and 4, and between pin 6 and 7). These higher frequency decoupling capacitors must be connected as close to the PLL501-01/-03 chip as possible, and preferably directly next to the PLL501-01/-03 pins. A series termination resistor of 33 may be used for the clock output. The input crystal must be connected as close to the chip as possible, and preferably directly next to the PLL50101/-03 pins. If a crystal with C L higher than 10pF is used, it will requires additional loading capacitors externally to complement the internal 10pF of the PLL501-01/-03: one between each crystal electrode and GND, as close to the crystal as possible, and preferably directly next to the crystal electrodes. Consult PhaseLink for recommended suppliers.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 5
PLL501-01/-03
VCXO Clock Generator IC
PACKAGE INFORMATION
8 PIN Narrow SOIC ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.55 0.15 0.35 0.19 4.80 3.81 5.84 0.41 1.27 BSC Max. 1.73 0.18 0.49 0.25 4.98 3.99 6.20 0.89 D E H
A 1 B e
A C L
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL501-0x S C
PART NUMBER TEMPERATURATRE
C=COMMERCIAL M=MILITARY
I=INDUSTRAL
S=SOIC
PACKAGE TYPE
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/10/01 Page 6


▲Up To Search▲   

 
Price & Availability of PLL501-03SM

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X